We architect dependable semiconductor test and verification strategies at system scale, combining CTO‑level guidance with silicon‑proven EDA and engineering expertise .
Helping deep‑tech teams and research organizations turn innovative ideas into reliable, production‑grade semiconductor systems .
Core Technical & Scientific Expertise
Strategic Technology Leadership & R&D Governance
Executive-level architectural arbitration, roadmap alignment, and governance of trade-offs across hardware, software, and data layers — bridging engineering execution with research and standards ecosystems.
EDAEDA Product & CAD Platform
Large-scale EDA systems, tool integration, HW/SW co-architecture, commercial platform scaling.
TestDFT & 3DIC Test Architectures
Hierarchical and 3DIC test strategies; IEEE 1838/1687/1500; cost–coverage trade-offs.
MemoryAdvanced Memory Test & Repair
SRAM & emerging NVM; yield optimization; lifecycle robustness; repair strategies.
VerificationSystem-Level Verification
Device → circuit → tool → data coherence; UVM-based verification; cross-layer validation.
IPTest, Reliability & Safety IP
Silicon-proven IP architecture (BIST/BISR/VIP), reusable and standards-aligned building blocks.
StandardsStandards & Technical Governance
IEEE 1149.x, 1500, 1687, 1838, 1450.6.x, 3405 — research-to-industry translation.
Applied AI for Semiconductor Engineering
AI/ML for test-time reduction, predictive failure analysis, yield learning acceleration, and data-driven engineering optimization — pragmatic, measurable, non-hype.
Services
Executive-grade engagements — grounded in deep technical expertise and standards-driven engineering practice.
Research Track
A developing institutional footprint combining applied research, standards contribution, and collaborative programs — strengthening over the next 24 months.
Contact
If you would like to collaborate or discuss a project, reach out.
contact@sis-str.com